
`include "defines.v"
//----------------------------------------------------------------
//Module Name : branch_comp.v
//Description of module:
//compare branch 
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/08/04	  
//----------------------------------------------------------------
module ysyx_210195_branch_comp(
	input	branch_en,							//分支比较使能
	input	[`REG_DATA_LEN-1:0]	op1,			
	input	[`REG_DATA_LEN-1:0]	op2,
	output	eq,				//equal
	output	ne,				//not equal
	output	lt,				//less than
	output	ge,				//greater than or equal
	output	ltu,			//无符号，less than
	output	geu				//无符号，greater than or equal
	);
wire [63:0] sub_res;
assign	sub_res = op1 - op2;	
assign	eq = branch_en ? (sub_res == 64'd0) : 1'b0;
assign	ne = branch_en ? (sub_res != 64'd0) : 1'b0;
assign	ltu = branch_en ? ((op1 < op2) ? 1'b1 : 1'b0) : 1'b0;
assign	geu = branch_en ? (((op1 > op2) | (op1 == op2)) ? 1'b1 : 1'b0) : 1'b0;
assign	ge = branch_en ? (sub_res[63] == 1'b0) : 1'b0;
assign	lt = branch_en ? (sub_res[63] == 1'b1) : 1'b0;



/*
always @(*)
begin
  if(branch_en)
  begin
		if((op1[`REG_DATA_LEN-1] == 1'b1) && (op2[`REG_DATA_LEN-1] == 1'b0))
			lt = 1'b1;
		else if((op1[`REG_DATA_LEN-1] == 1'b0) && (op2[`REG_DATA_LEN-1] == 1'b1))
			lt = 1'b0;
		else if((op1[`REG_DATA_LEN-1] == 1'b0) && (op2[`REG_DATA_LEN-1] == 1'b0))
			lt = (op1 < op2) ? 1'b1 : 1'b0;
		else
			lt = (op1 > op2) ? 1'b1 : 1'b0;
  end
  else
	lt = 1'b0;
end
always @(*)
begin
  if(branch_en)
  begin
		if((op1[`REG_DATA_LEN-1] == 1'b1) && (op2[`REG_DATA_LEN-1] == 1'b0))
			ge = 1'b0;
		else if((op1[`REG_DATA_LEN-1] == 1'b0) && (op2[`REG_DATA_LEN-1] == 1'b1))
			ge = 1'b1;
		else if((op1[`REG_DATA_LEN-1] == 1'b0) && (op2[`REG_DATA_LEN-1] == 1'b0))
			ge = ((op1 > op2) | (op1 == op2)) ? 1'b1 : 1'b0;
		else
			ge = ((op1 < op2) | (op1 == op2)) ? 1'b1 : 1'b0;
  end
  else
		ge = 1'b0;
end
*/
endmodule